1. Field of the Invention
The present invention relates to a communications circuit, and in particular, to an interface circuit permitting communication between circuits utilizing dissimilar logic families without requiring level translation.
2. Description of the Related Art
The Electronic Industry Association (EIA) and the Telecommunications Industry Association (TIA) are industry trade associations that have developed standards to simplify data communications. The TIA/EIA-232 (RS232) is one of the oldest and most widely known communication standards. It describes an unbalanced, unidirectional, point-to point interface. The RS232 communication standard has periodically been updated, with the latest revision being RS232-G.
The RS232 standard recognizes differential voltage signals ranging from −12V to +12V. At the time of adoption of the RS232 standard, the ±12V range provided a voltage spectrum broad enough to permit a variety of analog functions to be performed while the resulting signal remained comfortably above background noise. Of course, RS232 circuits were also utilized in digital applications, and an RS232 truth table is given below in TABLE A:
TABLE ARS232 Truth TableVOLTAGELOGIC STATE+3 V to +12 Vlow (=0)−3 V to −12 Vhigh (=1)
While the RS232 standard was once prevalent, over time the widespread use of digital technology dictated the implementation of logic families having voltage ranges different than that of the RS232. For example, reduced voltage ranges became available due to improvement in hardware having reduced background noise levels. Lower voltage ranges were also useful in preserving the thin and fragile gate dielectric structures of MOS devices increasingly employed in digital applications.
Accordingly, more recently implemented logic families utilize a narrower, single-ended voltage range. Voltage signals in these logic families are compatible with the requirements of MOS transistor operation, and reflect reduced noise levels typically encountered in existing digital technology. One such logic family is the transistor-transistor-logic family (TTL). A truth table for TTL is shown below in TABLE B:
TABLE BTTL Truth TableVOLTAGELOGIC STATE0 V to +0.8 Vlow (=0)+2.4 V to +5.0 Vhigh (=1)
In recent years, several factors have prompted adoption of logic families featuring even narrower voltage ranges than the TTL logic family. One factor is an increased emphasis on portable applications requiring reduced power consumption in order to conserve battery life. Another factor is the ever-shrinking size of MOS devices and the corresponding need to preserve the integrity of thin gate dielectric structures in the presence of applied voltages.
While technology is evolving away from the RS232 communications standard, this standard is still employed in a wide variety of applications. Therefore, there is a need in the art for an interface circuit permitting communication to occur between devices utilizing the RS232 standard and devices utilizing the various other logic families.
FIG. 1 shows a schematic diagram of a conventional interface circuit positioned between a host device featuring an RS232 port, and a peripheral device controlled by a microcontroller utilizing the TTL logic family. Communication circuit 100 includes host device 101 featuring RS232 port 102 having transmit data (TXD) pin 104 and receive data (RXD) pin 106. TXD pin 104 and RXD pin 106 emit and receive, respectively, signals in which between +3V and +12V are interpreted as a logical low state (=0) and between −3V and −12V are interpreted as a logical high state (=1).
TTL microcontroller 107 of peripheral device 108 features eight pin parallel port 109. Pins 110 of port 109 emit and receive respectively, voltage signals where between 0V and +0.8V represents a logical low state (=0) and between +2.4V and +5V represents a logical high state (=1).
In order to permit communication to occur between host device 101 and peripheral device 107, interface circuit 100 further includes level shift/buffer 116 and universal asynchronous receiver/transmitter (UART) 118.
The role of level shift/buffer 116 is to perform level translation on the voltage signals being exchanged between host device 101 and peripheral device 107, such that voltage signals correlating to appropriate logic values are communicated between the devices. Thus, where a logical low (+0V) TTL signal is being transmitted from pin 112 of TTL peripheral device 107, level shift/buffer 116 converts this signal to the +12V logical low value understood by RS232 device 101. Conversely, where a logical high value of −12V is being transmitted from RS232 port 102, level shift/buffer 116 converts this signal to the +5V logical high value understood by TTL peripheral device 107. A level shift/buffer commonly employed for this purpose is National Semiconductor Corporation part No. DS14C535, which requires connection to power supplies of both the +5V and ±12V variety.
The role played by UART 118 in permitting communication between the RS232 and non-RS232 devices two-fold.
UART 118 performs serial-to-parallel or parallel-to-serial conversion of signals exchanged between host RS232 device 101 and peripheral TTL device 107, such that each device receives a signal in the appropriate form. Thus UART 118 assembles a serial stream of one-bit signals transmitted from RS232 port 102, into discrete eight-bit words recognized at parallel port 109 by peripheral device 107. Conversely, where an eight-bit data word is being transmitted in parallel form from pins 110 of peripheral device 107, UART 118 converts this parallel word into a serial stream of one-bit signals recognized at RS232 port 102 of host device 101. A UART commonly employed for use in interface applications is National Semiconductor Corporation part No. PC16550D.
The second function performed by UART 118 is to coordinate timing of transmission of the serial stream of electrical signals between the devices. Upon receiving a START bit from a transmitting device, UART 118 synchronizes receipt of the serial data stream at regular, predetermined intervals, enabling the serial data to be properly recognized.
While the conventional communication interface circuit shown in FIG. 1 is suitable for some applications, it suffers from a number of disadvantages. One disadvantage is a high part count. Specifically, the conventional interface circuit requires separate level shift/buffer and UART components described above. These components each contribute expense and complexity to the interface circuit. Another disadvantage of the conventional circuit is that the level/shift buffer component must be connected with power supplies of both devices in order to perform level translation. A further disadvantage is that the UART component is typically bulky and consumes precious space on the circuit board.
Therefore, there is a need in the art for a compact, simple, and inexpensive communication interface circuit between devices utilizing different logic families which does not require separate components to perform level translation and parallel/serial conversion.